1. Field of the Invention
The present invention relates generally to integrated circuit packaging, and in particular to a structure and method for minimizing the lead length between a passive electronic device and an integrated circuit.
2. Description of Related Art
Semiconductor devices having high and dense lead counts and operating at high speeds require very short leads to ensure noiseless signal propagation. Noise can be introduced onto a lead by other nearby signal leads. Additionally, passive devices or components, such as resistors, capacitors, inductors and filters, add to the length of signal leads within an assembly. As used herein, the term xe2x80x9csemiconductor devicexe2x80x9d or xe2x80x9cdevicexe2x80x9d refers to an integrated circuit chip or die containing circuitry. The xe2x80x9ccarrierxe2x80x9d refers to the substrate material upon which the device is attached and contains internal circuitry that is used to interface the device with other electronic components. The xe2x80x9csemiconductor device assemblyxe2x80x9d or xe2x80x9cassemblyxe2x80x9d refers to the semiconductor device plus associated carrier containing the device. The xe2x80x9cpassivexe2x80x9d refers to resistors, inductors, filters, capacitors and any combination attached to the carrier and/or device as a component of the assembly. A xe2x80x9cboardxe2x80x9d is a structure that is used to hold a plurality of carriers.
The lead length effect is highly affected by the capacitor type passive component. It is highly desirable to locate the capacitors as close to the semiconductor device as possible. It is a common practice to mount capacitors external to the semiconductor device. In some carriers, the capacitors may be mounted on the same plane as the device but off to one side or another. Another carrier structure might attach the capacitor within a socket or cavity on the carrier. In either case, the capacitor is xe2x80x9cremotelyxe2x80x9d located away from the semiconductor device. As the distance from the capacitor to the semiconductor device increases, the capacitor""s efficiency and effectiveness are adversely affected. Problems that can occur include stray inductances, ground plane bounce, and voltage surges.
Attempts in the prior art to reduce lead lengths has not resolved these problems. For example, U.S. Pat. No. 5,210,683 discloses an assembly for mounting a capacitor, external to a semiconductor device, within a well or cavity that is formed in the assembly in close proximity to the device such that it is located within the assembly and thereby somewhat reducing the lead or via length. However, the major problem of connectivity to the device, without electrical noise still exists with this structure.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a structure and method for minimizing the lead length between a passive electronic component, a carrier or board, and an electronic device.
It is another object of the present invention to provide a structure and method to minimize the distance between a passive electronic device and a semiconductor device.
A further object of the invention is to provide a method and structure to minimize the length of signal leads within a semiconductor device assembly.
It is yet another object of the present invention to provide a method and structure to minimize the ability of electrical noise to be induced onto nearby signal leads.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one skilled in the art, are achieved in the present invention which is directed to, in a first aspect, a method of electrically connecting a passive electronic component to a semiconductor substrate and a semiconductor device whereby the lead lengths between the passive electrical component, the substrate and the device are minimized. In the preferred embodiment, the method comprises forming a first cavity in a layer of a semiconductor substrate. The first cavity has at least one electrical termination pad on one of its surfaces. A first passive electrical component is electrically connected in the first cavity, the electrical connection being made between at least one electrical connection point on a surface of the first component and the electrical termination pad of the cavity. A semiconductor device is placed over the first cavity and first component such that an electrical termination pad on the semiconductor device makes an electrical connection with a second connection point on the first component.
In the preferred embodiment, a second cavity having at least one electrical termination pad is also formed in the substrate and a second passive electrical component is electrically connected to an electrical connection point in the second cavity. In the most preferred embodiment, a number of cavities are formed in the substrate surface, each one being adapted to have a passive electrical component mounted therein with an electrical connection being made between termination pads in the cavity and electrical connection points on the component.
In the preferred embodiment, the electrical connection points on the passive component are solder bumps and the electrical connections are made using controlled collapse chip connection technology. In the most preferred embodiment, the electrical connection points are located on opposing sides of the component.
In another aspect, the method may include forming a multilevel cavity adapted to hold a plurality of passive electrical components.
In the preferred embodiment, the substrate includes a plurality of layers including at least one layer of internal circuitry used to interface the passive components with at least one other electrical device. It is also preferred that the method include electrically connecting the substrate to at least one passive electrical component mounted in a cavity formed in an electronic circuit board.
In another aspect, the present invention is directed to a structure for electrically connecting a discrete electrical component between a semiconductor substrate and an electronic semiconductor device whereby the lead length of the discrete electrical device is minimized. The structure comprises at least one cavity formed in a semiconductor substrate, and at least one discrete electrical component located in the cavity. The electronic component is electrically connected to the substrate and a semiconductor device positioned over the cavity. In the preferred embodiment, the cavity includes at least one electrical termination pad on a surface of the cavity which is electrically connected to an electrical connection point on the electrical component. In the preferred embodiment, the electrical connection points on the component are located on opposing sides of the component. It is preferred that the electrical connection points are solder bumps.
In the preferred embodiment, the component is electrically connected to the substrate and the semiconductor device, most preferably using solder connection technology. It is also preferred that the solder connection technology is controlled collapse connection technology.
The cavity may also comprise a multilevel cavity adapted to contain a plurality of discrete components electrically connected to the substrate semiconductor device. In the preferred embodiment, the substrate layer includes at least one layer of internal circuitry used to interface the discrete electrical component with at least one other electrical device. In the preferred embodiment, the electronic circuit board may have at least one cavity formed therein adapted to contain at least one discrete electrical component electrically connected to the circuit board and the substrate.